AD4002 datasheet(30/39 Pages) AD

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AD4002/AD4006/AD4010

Data Sheet

Rev. A | Page 30 of 39

CS MODE, 3-WIRE TURBO MODE

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host.

Turbo mode allows lower SCK frequencies by increasing the time

that the ADC conversion result can be clocked out. The AD4002

can achieve a throughput rate of 2 MSPS only when turbo mode is

enabled and using a minimum SCK rate of 75 MHz (see the Serial

Clock Frequency Requirements section). The connection

diagram is shown in Figure 51, and the corresponding timing

diagram is shown in Figure 52.

To enable turbo mode, set the turbo mode enable bit in the

configuration register to 1 (see Table 12). This mode replaces the

3-wire with busy indicator mode when turbo mode is enabled.

Writing to the user configuration register requires SDI to be

connected to the digital host (see the Register Read/Write

Functionality section). When turbo mode is enabled, the

conversion result read on SDO corresponds to the result of the

previous conversion.

When performing conversions in this mode, SDI must be held

high. A CNV rising edge initiates a conversion and forces SDO to

high impedance. The user must wait tQUIET1 time after the CNV

rising edge before bringing CNV low to clock out the previous

conversion result. When the conversion is complete (after tCONV),

the AD4002/AD4006/AD4010 enter the acquisition phase and

power down.

When CNV goes low, the MSB is output to SDO. The remaining

data bits are clocked by subsequent SCK falling edges. The data is

valid on both SCK edges. Although the rising edge can capture the

data, a digital host using the SCK falling edge allows a faster

reading rate, provided it has an acceptable hold time, as dictated by

tHSDO (see Table 2). If the status bits are not enabled, SDO returns to

high impedance after the 18th SCK falling edge. If the status bits are

enabled, they are shifted out on the 19th through the 24th SCK

falling edge (see the Status Bits section). SDO returns to high

impedance after the final SCK falling edge, or when CNV goes high

(whichever occurs first). The user must also provide a delay of

tQUIET2 between the final SCK falling edge and the next CNV rising

edge to ensure specified performance.

AD4002/

AD4006/

AD4010

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

DATA OUT

Figure 51. CS Mode, 3-Wire Turbo Mode Connection Diagram

SDI = 1

tCYC

CNV

ACQUISITION

tACQ

tSCK

tSCKL

CONVERSION

SCK

D15

D16

D17

SDO

tEN

tHSDO

tDSDO

tDIS

tSCKH

tQUIET1

QUIET2

CONV

Figure

52. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (Status Bits Not Shown)

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