LTC6801 datasheet(13/28 Pages) AD

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LTC6801

Rev. F

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APPLICATIONS INFORMATION

ENABLE INPUTS

In order to support stacked operation, the LTC6801 is

enabled through a differential signal chain encompassing

the EIN/EIN, EOUT/EOUT, and SIN/SIN pins.

The LTC6801 will be enabled if a differential square wave

with a frequency between 2kHz and 40kHz is applied at

EIN/EIN. Otherwise, the LTC6801 will default to a low

power idle mode.

If the differential signal at SIN/SIN is not equal in fre-

quency to the differential signal output at EOUT/EOUT,

the LTC6801 will be enabled but SOUT will be held at 0V

and SOUT will be held at VREG.

For the simplest operation in a single chip configuration,

EOUT should be connected directly to SIN and EOUT

should be connected directly to SIN, and a square wave

with a frequency between 2kHz and 40kHz should be

applied differentially to EIN and EIN. For enable clock fre-

quencies up to 10kHz, a single-ended square wave with

a 5V swing may be used at EIN while a 1nF capacitor is

connected from EIN to V–.

STATUS OUTPUT

If the chip is properly enabled (EIN/EIN, SIN/SIN are the

same frequency), all cells are within the undervoltage

and overvoltage thresholds, and the voltage at VTEMP1

and VTEMP2 is over one half VREF, the differential output

at SOUT/SOUT will toggle at the same frequency and in

phase with the signal at EIN/EIN. Otherwise, SOUT will be

low and SOUT will be high.

The maximum delay between when a bad cell voltage

occurs and when it is detected depends on the measure-

ment duty cycle setting. The SOUT clock turns on or off

at the end of each measurement cycle. Figure 4 shows the

maximum detection delay in continuous monitor mode

(DC pin tied to VREG).

Note: If an internal self test occurs immediately after the

fault, the maximum detection delay will be increased by

an additional measurement cycle time.

FAULT PROTECTION

Overview

Care should always be taken when using high energy

sources such as batteries. There are countless ways that

systems can be [mis-]configured during the assembly

and service procedures that can impact a battery’s long

term performance. Table 6 shows various situations to

consider when planning protection circuitry.

Battery Interconnection Integrity

Please note: The last condition shown in the FMEA table

could cause catastrophic IC failures. In this case, the bat-

tery string integrity is lost within a cell group monitored by

an LTC6801. This condition could place excessive stress

on certain cell input signal clamp-diodes and probably

lead to IC failure. If this scenario seems at all likely in a

particular application, series fuses and parallel Schottky

diodes should be connected as shown in Figure 5 to limit

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