LTC6801

16

Rev. F

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Table 6. Failure Mechanism Effect Analysis (FMEA)

SCENARIO

EFFECT

DESIGN MITIGATION

Cell input open-circuit (random)

Power-up sequence at IC inputs

Clamp diodes at each pin to V+ & V– (within IC)

provide alternate PowerPath.

Cell input open-circuit (random)

Differential input voltage overstress

Zener diodes across each cell voltage input pair

(within IC) limit stress.

Top cell input connection loss (V+)

Power will come from highest connected cell

input

Clamp diodes at each pin to V+ and V– (within

IC) provide alternate PowerPath. Error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

Bottom cell input connection loss (V–)

Power will come from lowest connected cell input Clamp diodes at each pin to V+ and V– (within

IC) provide alternate PowerPath. Error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

Power input disconnection

(amongst stacked units)

Loss of supply connections

Clamp diodes at each pin to V+ and V– (within

IC) provide alternate PowerPath. Error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

Status link disconnection

(between stacked units)

Break of “daisy chain” communication

(no stress to ICs)

Daisy chain will be broken and error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

Short between any two configuration inputs

Power supplies connected to pins will be shorted If VREF or VREG is shorted to V–, supply will

be removed from internal circuitry and error

condition will be indicated by all upstream and

downstream units (no clock on SOUT/ SOUT). If

VREF is shorted to VREG, a self test error will be

flagged.

Open connection on configuration input

Control input will be pulled towards positive or

negative potential depending on pin

Control input will be pulled to a more stringent

condition (larger number of channels, higher UV

threshold, lower OV threshold, shorter duty cycle,

etc. ensuring either more stringent monitoring or

error condition will be indicated by all upstream

and downstream units (no clock on SOUT/

SOUT).

Cell-pack integrity, break between stacked units

Daisy-chain voltage reversal up to full stack

potential

Full stack potential may appear across status/

enable isolation devices, but will not be seen by

the IC. isolation capacitors should therefore be

rated to withstand the full stack potential.

Cell-pack integrity, break within stacked unit

Cell input reverse overstress

Add battery tap fuses and Schottky diodes in

parallel with the cell inputs to limit stress on

IC. Diode and connections must handle current

sufficient to open fuse

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