LS1012A datasheet(16/39 Pages) NXP

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Table 2-1. FRWY-LS1012A power supply devices (continued)

Sourc

volta

rail

Output

voltage rail

Reference

designator

Vendor

Device

Description

VCC_

3V3

VCC_0V9

VCC_1V8

VCC_1V35

VCC_VREF

VCC_POVDD

VCC_2V5

VCC_EVDD

NXP

MC34VR5100A1EP Power supply for:

• LS1012A power supplies

• 1.35 V for DDR3L memory

• SerDes, USB

• 1.8 V voltage for QSPI memory, SAI2 port,

general I/O

• 2.5 V for Ethernet PHYs

2.2.3 Power-ON

The FRWY-LS1012A is powered using 5 V DC power adapter through a DC power jack.

The DC power adapter provides 5 V DC voltage. The 5 V voltage powers primary power

supply regulator U7. U7 provides power supply to the secondary regulator U8, the

onboard SGMII PHYs, and the NGFF slot. The secondary regulator, U8, generates power

supply for peripherals, such as QSPI flash memory and LS1012A power supplies.

Table 2-2 describes the Power-ON sequence as implemented on the FRWY-LS1012A.

Table 2-2. Power-ON process

Step

Indication

Specifics

Description

• Power supply provided by DC Jack, J31

• Acts as source PS for secondary regulator MC34713

3V3

• 3.3 V power supply for onboard SGMII PHYs and LS1012A

supplies: EVDD and USB_HVDD

• Acts as source PS for secondary regulators VR5100

1V8, 1V35

Power supplies provided by secondary regulator VR5100

• Provides power to peripherals and LS1012A IO and PLL

supplies (AVDD_PLAT, AVDD_CGA1, TH_VDD,

AVDD_SD1_PLL1, AVDD_SD1_PLL2, OVDD, XOSC_OVDD,

USB_SVDD, USB_SDVDD, G1VDD, VREF, SVDD, and XVDD)

0V9

• LS1012A core supplies: VDD

Red LED (D3)

• Reset LED is deasserted.

2.2.4 Voltage regulation

Power supplies

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

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