LS1012A datasheet(25/39 Pages) NXP

25 / 39 page

2.10 USB interface

The FRWY-LS1012A board supports one SuperSpeed USB 2.0/3.0 port - configured as

On-The-Go (OTG) with a Micro-AB connector. Based on the OTG configuration, the

PHY can either operate in the Type-A or Type-B mode.

The following figure shows the USB 2.0/3.0 PHY architecture on the FRWY-LS1012A.

LS1012A

USB3 Micro - AB

USB1_DRVVBUS

USB1_PWRFAULT

USB1_VBUS

90 Ohm Diff. Impedance

USB1_DP,DM

USB1_TXP,TXM

USB1_RESREF

USB1_RXP,RXM

USB1_ID

NX5P3090UK

<=1.5A

USB1_5V

Figure 2-8. USB 2.0/3.0 PHY architecture

2.11 I2C ports

The FRWY-LS1012A support one I2C bus:

• The LS1012A I2C1 is attached to the local devices on the FRWY-LS1012A.

• The level shifter device (NTSX2102GU8H) is used on the FRWY-LS1012A I2C1

bus, to convert the LS1012A 1.8 V to 3.3 V signals for the I2C devices, on the

mikroBUS click connectors.

• The I2C1 bus has one possible master - LS1012A processor.

Chapter 2 FRWY-LS1012A Functional Description

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

NXP Semiconductors

LS1012A Datasheet(PDF) 25 Page - NXP Semiconductors