LS1012A datasheet(8/39 Pages) NXP

8 / 39 page

Table 1-3. FRWY-LS1012A features (continued)

Feature

Specification

Description

I2C

• One I2C bus with connectivity to mikroBUS click headers

and audio device

Debug features

• Arm Cortex® 10-pin JTAG connector for LS1012A

• CMSIS DAP through K20 microcontroller

Package

• Package type is 9.6 mm x 9.6 mm x 0.805, 211 Flip Chip

Land Grid Array (FC-LGA)

Clocks

• 25 MHz Oscillator for LS1012A

• 25 MHz Oscillator for audio codec

• 25 MHz crystals for 2 SGMII PHYs

• 100 MHz reference clock for M.2 NGFF slot

• 8 MHz Crystal for K20

• 24 MHz for SC16IS740IPW SPI to Dual UART bridge

Power supplies

• 5 V input supply from power adapter

• 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and

other board interfaces

1. For details about features of the LS1012A SoC, see QorIQ LS1012A Family Reference Manual.

1.5 FRWY-LS1012A block diagram

Figure 1-1 shows the FRWY-LS1012A block diagram.

FRWY-LS1012A block diagram

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

NXP Semiconductors

LS1012A Datasheet(PDF) 8 Page - NXP Semiconductors