LS1012A datasheet(29/39 Pages) NXP

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LS1012A

SDHC1_DAT[0:3]

SDHC1_CMD

SDHC1_CD_B

SDHC1_DAT[0:3], SDHC1_CMD

SDHC1_CLK

EVDD

SDHC1_VSEL

*PORConfig-> cf g_pbi_dis

SDHC1_VSEL

* *Bootsat 3.3V, can

dynamically switch to

1.8V

Notes:

SDHC1:

- SDHC1 boots at 3.3V, can dynamically switch to 1.8V

controlled by SDHC1_VSEL.

- SD Card shall not support Write Protect Feature

*PORConfig-> cf g_t est _port_mux_sel

3V3

1V8

EVDD

FPF132

1UCX

Figure 2-10. SDHC1 interface

2.16 JTAG port

The FRWY-LS1012A consists of the LS1012A SoC and the K20 microcontroller, each

of which have dedicated debug connectors.

• J9 and J10 are used by external debuggers, such as CWTAP, DSTREAM to debug

LS1012A and K20 respectively.

NOTE

Ensure that the Pin number 1 of the JTAG cable is

connected to the Pin number 1 of the onboard connector,

J9.

• Apart from the JTAG connectors, the K20 MCU can be used as a CMSIS DAP on

the FRWY-LS1012A. The CMSIS DAP provides low speed debug functionality for

LS1012A.

2.16.1 CMSIS-DAP

Chapter 2 FRWY-LS1012A Functional Description

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

NXP Semiconductors

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