LS1012A datasheet(23/39 Pages) NXP

23 / 39 page

MDIO

MDC

Ethernet Controller

LS1012A

3V3

SGMII

MDI_0_P/N

MDI_1_P/N

MDI_3_P/N

MDI_2_P/N

INTB

PHYRSTB

DVDD33

4.7K

PHY

SUPPORT

MODE: SGMII

RJ-45

1Gbps

100Mbps

1.1V

AVDDL

DVDDL

AVDD33

0 ohm

AR8033

Notes and Assumptions:

- MAC connected to Serdes lane B is the same MAC connected to the RGMII interface.

so RGMII and SGMII ( lane B) can not be use at a time.

- If the Serdes is configured for 2 SGMII interfaces, then the RGMII interface is unused

(tristated unless the pinmuxing control register is configured for functionality other than

EC1 RGMII).

TX_P/N

RX_P/N

HSIP/N

HSOP/N

EM1_MDC

EM1_MDIO

Transfo rmer

Voltage

Translator

1.8V 3.3V

Voltage

Translator

2.5V

1.8V

VVDIO_REG

VVDH_REG

2V5

DUT_PORST_B

Figure 2-6. SGMII PHY2

Table 2-8. Hardware bootstrap settings for Ethernet PHYs

Setting

Description

PHY_AD[2:0] = 010 (for SGMII PHY1)

PHY_AD[2:0] = 001 (for SGMII PHY2)

PHY Addr = 0b00010 (for SGMII PHY1)

PHY Addr = 0b00001 (for SGMII PHY2)

MODE[3:0]=0001

SGMII <=> UTP (1000 BASE-T, SGMII)

Chapter 2 FRWY-LS1012A Functional Description

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

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