LS1012A datasheet(19/39 Pages) NXP

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2.4 Clocks

The architecture of the FRWY-LS1012A clocks is shown in the following figure.

LS1012A

EXTAL

ETH SGMII

PHY

AR8033

ETH SGMII

PHY

AR8033

8 MHz

Crystal

K20

Audio

SGTL5000

25MHz

SPI to UART

Bridge

SC16IS740IPW

24MHz

25MHz

M.2 Type-E

NGFF

Connector

100MHz

25MHz

100MHz

SD1_REF_CLK1_N

SD1_REF_CLK1_P

PCIe Gen Clock

Buffer 2-OUT

Si52112-B3

Figure 2-4. Clock architecture

The following table summarizes the FRWY-LS1012A clock distribution.

Table 2-6. FRWY-LS1012A clocks

Clock

Frequency

Destination

Device

EXTAL (Bypass mode)

25 MHz

Input clock for SoC

Oscillator

SD1_REF_CLK1_P/N

100 MHz

Reference clock for

LS1012A SerDes controller

25 MHz crystal clock and PCIe clock

generator, Si52112-B3:

• 2 output PCIe Gen1 Clock Generator

• Low power consumption

• Phase jitter - 1.4 ps

• Skew outputs - 60 ps

• Output clock frequency (min/max) -

100 MHz

PEXM2_REFCLK_P/N

100 MHz

Reference clock for NGFF

Slot

ETH1_XTALIN,

ETH1_XTALOUT

25 MHz

Crystal clock for the SGMII

PHY1

Crystal

Table continues on the next page...

Chapter 2 FRWY-LS1012A Functional Description

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