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XC2000 Datasheet(PDF) 101 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 101 Page - Infineon Technologies AG |
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101 / 110 page  XC2287 / XC2286 / XC2285 XC2000 Family Derivatives Electrical Parameters Preliminary Data Sheet 99 V0.91, 2007-02 Draft Version Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. Asynchronous READY puts no timing constraints on the input signal but incurs one waitstate minimum due to the additional synchronization stage. The minimum duration of an asynchronous READY signal to be safely synchronized must be one CLKOUT period plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the next following bus cycle is READY-controlled, an active READY signal must be disabled before the first valid sample point for the next bus cycle. This sample point depends on the programmed phases of the next following cycle. |
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