XC2000 datasheet(97/110 Pages) INFINEON

97 / 110 page

XC2287 / XC2286 / XC2285

XC2000 Family Derivatives

Electrical Parameters

Preliminary

Data Sheet

V0.91, 2007-02

Draft Version

Table 22

External Bus Cycle Timing for 4.5 V

≤ V

DDP ≤ 5.5 V

(Operating Conditions apply)

Parameter

Symbol

Limits

Unit

Note

Min.

Typ.

Max.

Output valid delay for:

RD, WR(L/H)

10 CC

–

Output valid delay for:

BHE, ALE

11 CC

–

Output valid delay for:

A23 … A16, A15 … A0 (on P0/P1)

12 CC

–

Output valid delay for:

A15 … A0 (on P2/P10)

13 CC

–

Output valid delay for:

14 CC

–

Output valid delay for:

D15 … D0 (write data, MUX-mode)

15 CC

–

Output valid delay for:

D15 … D0 (write data, DEMUX-

mode)

16 CC

–

Output hold time for:

RD, WR(L/H)

20 CC

8ns

Output hold time for:

BHE, ALE

21 CC

8ns

Output hold time for:

A23 … A16, A15 … A0 (on P2/P10)

23 CC

8ns

Output hold time for:

24 CC

8ns

Output hold time for:

D15 … D0 (write data)

25 CC

8ns

Input setup time for:

READY, D15 … D0 (read data)

30 SR

–ns

Input hold time for:

READY, D15 … D0 (read data)

1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read

data can be removed after the rising edge of RD.

31 SR

-4

–ns

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