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ECP2 Datasheet(PDF) 357 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 357 Page - Lattice Semiconductor |
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357 / 386 page  4-256 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet J9 NC - NC - K10 NC - NC - K11 NC - NC - K12 NC - NC - K13 NC - NC - K23 NC - NC - K24 NC - NC - K25 NC - NC - K26 NC - NC - L11 NC - NC - L12 NC - NC - L13 NC - NC - L14 NC - NC - L21 NC - NC - L22 NC - NC - L23 NC - NC - L24 NC - NC - L25 NC - NC - L26 NC - NC - M11 NC - NC - M24 NC - NC - M25 NC - NC - M6 NC - NC - M8 NC - NC - N10 NC - NC - N11 NC - NC - P10 NC - NC - P25 NC - NC - P26 NC - NC - R9 NC - NC - T11 NC - NC - U11 NC - NC - W11 NC - NC - Y10 NC - NC - Y11 NC - NC - R15 VCCPLL - VCCPLL - R20 VCCPLL - VCCPLL - Y15 VCCPLL - VCCPLL - Y20 VCCPLL - VCCPLL - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70, and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE LFE2M100E/SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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