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7477 Datasheet(PDF) 19 Page - Renesas Technology Corp |
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7477 Datasheet(HTML) 19 Page - Renesas Technology Corp |
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19 / 48 page ![]() 18 MITSUBISHI MICROCOMPUTERS 7477/ 7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit or receive buffer. Fig. 8 Clock synchronous serial I/O block diagram Fig. 9 Operation of clock synchronous serial I/O function Transfer shift clock (1/8 to 1/8192 of the internal clock, or an external clock) Serial output TxD Serial input RxD Receive enable signal SRDY Write signal to receive/transmit buffer D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt request (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt request (RI) is set when the receive buffer full flag (RBF) becomes “1”. Data bus Data bus Receive buffer register Clock control circuit Serial I/O control register Fall detect Serial I/O status register F/F 1/4 1/4 1/4 Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Receive interrupt request (RI) Serial I/O synchronous clock selection bit (SCS) Frequency dividing ratio 1/(n+1) P16 P14 Shift clock P15 P17 Clock control circuit Receive shift register Transmit shift register Transmit buffer register TXD SRDY SCLK RXD f(XIN) SRDY Address 00E016 Address 00E216 Address 00E016 Address 00E116 Address 00E416 CSS TE RE SIOE Baud rate generator TIC Shift clock |
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