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7477 Datasheet(PDF) 26 Page - Renesas Technology Corp |
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7477 Datasheet(HTML) 26 Page - Renesas Technology Corp |
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26 / 48 page  25 MITSUBISHI MICROCOMPUTERS 7477/ 7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 18 Timing diagram at reset Fig. 16 Example of reset circuit Fig. 17 Internal state of microcomputer at reset (1) Port P0 direction register (C116) … (2) Port P1 direction register (C316) … (3) Port P4 direction register (C916) … (4) P0 pull-up control register (D016) … (5) P1–P5 pull-up control register (Note 1) (D116) … (6) Edge selection register (EG) (D416) … (7) A-D control register (D916) … (8) Serial I/O status register (E116) … (9) Serial I/O control register (E216) … (10) UART control register (E316) … (11) Timer 12 mode register (T12M) (F816) … (12) Timer 34 mode register (T34M) (F916) … (13) Timer mode register 2 (TM2) (FA16) … (14) CPU mode register (CM) (FB16) … (15) Interrupt request register 1 (FC16) … (16) Interrupt request register 2 (FD16) … (17) Interrupt control register 1 (FE16) … (18) Interrupt control register 2 (FF16) … (19) Program counter (PCH) … (PCL) … (20) Processor status register (PS) … 0016 0016 00 0 0 00 0 0 00 0 0 0 0 01 0 0 0 0 0 00 00 0 00 0 0 00 0 0 00 0 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 1 0016 0016 0016 0016 Contents of address FFFF16 Contents of address FFFE16 Notes 1 : This address is allocated P1–P4 pull-up control register for the 7477 group. Bit 6 is not used. 2 : Since the contents of both registers other than those listed above (including timers and the transmit/receive buffer register) are undefined at reset, it is necessary to set initial values. Address RESET CIRCUIT The 7477/7478 group is reset according to the sequence shown in Figure 18. It starts the program from the address formed by using the content of address FFFF16 as the high order address and the content of the address FFFE16 as the low order address, when the RESET pin is held at “L” level for no less than 2 µs while the power voltage is in the recommended operating condition and then re- turned to “H” level. The internal initializations following reset are shown in Figure 17. Example of reset circuit is Figure 16. Immediately after reset, timer 3 and timer 4 are connected, and counts the f(XIN) divided by 16. At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The reset is cleared when timer 4 overflows. RESET VCC 7477/7478 group 00, S 00, S-1 00, S-2 FFFE16 FFFF16 ADH,L PCH PCL PS ADL ADH XIN φ RESET Internal Address Data SYNC 32768 counts of f(XIN) Reset address from the vector table Notes 1 : Frequency relation of X IN and φ is f(XIN)=2·φ. 2 : The mark “?” means that the address is changeable depending upon the previous state. RESET ? ? ? ? |
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