SH7149 datasheet(124/1022 Pages) RENESAS

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Section 5 Exception Handling

Rev. 3.00 May 17, 2007 Page 80 of 974

REJ09B0229-0300

Be certain to always perform power-on reset exception handling when turning the system power

on.

Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that

a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the

power-on reset state.

The frequency control register (FRQCR) in the clock pulse generator (CPG) and the watchdog

timer (WDT) registers are not initialized by the reset signal generated by the WDT (these registers

are only initialized by a power-on reset from the

RES pin).

If a reset caused by the signal input on the

RES pin and a reset caused by a WDT overflow occur

simultaneously, the

RES pin reset has priority, and the WOVF bit in WTCSR is cleared to 0.

When the power-on reset exception handling caused by the WDT is started, the CPU operates as

follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in the PC and SP, then the

program starts.

5.2.3

Manual Reset

When the

RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset

state. To reliably reset the LSI, the

MRES pin should be kept at low for at least the duration of the

oscillation settling time that is set in WDT when in software standby mode (when the clock is

halted) or at least 20 t

cyc when the clock is operating. During manual reset, the CPU internal status

is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters

manual reset status in the middle of a bus cycle, manual reset exception processing does not start

until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once

MRES

is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus

cycle ends. (Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for

the status of individual pins during manual reset mode.

In the manual reset status, manual reset exception processing starts when the

MRES pin is first

kept low for a set period of time and then returned to high. The CPU will then operate in the same

procedures as described for power-on resets.

SH7149 Datasheet(PDF) 124 Page - Renesas Technology Corp

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