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HD64F2621 Datasheet(PDF) 43 Page - Renesas Technology Corp |
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HD64F2621 Datasheet(HTML) 43 Page - Renesas Technology Corp |
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43 / 1069 page ![]() Section 1 Overview Rev. 5.00 Jan 10, 2006 page 19 of 1042 REJ09B0275-0500 Type Symbol I/O Pin Name Function Operating mode control MD2 to MD0 Input Mode pins These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. Inputs at these pins should not be changed during operation. MD2 MD1 MD0 Operating Mode 000 — 1 — 10 — 1 — 100Mode 4 1 Mode 5 1 0 Mode 6 1 Mode 7 System control RES Input Reset input When this pin is driven low, the chip is reset. STBY Input Standby When this pin is driven low, a transition is made to hardware standby mode. BREQ Input Bus request Used by an external bus master to issue a bus request to the chip. BREQO Output Bus request output External bus request signal used when an internal bus master accesses external space in the external bus- released state. BACK Output Bus request acknowledge Indicates that the bus has been released to an external bus master. FWE Input Flash write enable Pin for use by flash memory Interrupts NMI Input Nonmaskable interrupt Requests a nonmaskable interrupt. If this pin is not used, it should be fixed high. IRQ5 to IRQ0 Input Interrupt request 5 to 0 These pins request a maskable interrupt. Address bus A23 to A0 Output Address bus These pins output address signals. |
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