HD64F2621 datasheet(85/1069 Pages) RENESAS

85 / 1069 page

Section 2 CPU

Rev. 5.00 Jan 10, 2006 page 61 of 1042

REJ09B0275-0500

Exception handling state

Bus-released state

Hardware standby mode*

Software standby mode

Reset state*

Sleep mode

Power-down state*

Program execution state

End of bus request

Bus request

Interrupt

request

External interrupt request

RES= High

STBY= High, RES= Low

End

bus

request

Bus

request

SLEEP

instruction

with

SSBY = 0

SLEEP

instruction

with

SSBY = 1

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs whenever

RES

goes low. A transition can also be made to the reset state when the watchdog timer overflows.

From any state, a transition to hardware standby mode occurs when

STBY goes low.

Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode in the

H8S/2626 Group. See section 21B, Power-Down Modes [H8S/2626 Group].

Reset state

Figure 2.15 State Transitions

2.8.2

Reset State

When the

RES input goes low all current processing stops and the CPU enters the reset state. All

interrupts are masked in the reset state. Reset exception handling starts when the

RES signal

changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,

Watchdog Timer.

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