HD64F2621 datasheet(30/1069 Pages) RENESAS

30 / 1069 page

Section 1 Overview

Rev. 5.00 Jan 10, 2006 page 6 of 1042

REJ09B0275-0500

1.2

Internal Block Diagram

Figures 1.1 and 1.2 show internal block diagrams of the H8S/2623 Group and H8S/2626 Group.

Port D

PA5

PA4

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9/TIOCB3

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/

IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/

IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

P97/AN15

P96/AN14

P95/AN13

P94/AN12

P93 / AN11

P92 / AN10

P91 / AN9

P90 / AN8

PF7/

PF6/

PF5/

PF4/

HWR

PF3/

LWR/ADTRG/IRQ3

PF2/

WAIT/BREQO

PF1/

BACK

PF0/

BREQ/IRQ2

ROM

(Mask ROM,

flash memory)

PC break controller

(2 channels)

RAM

WDT

× 1 channel

TPU

SCI

× 3 channels

HCAN

× 1 channel

A/D converter

PPG

MD2

MD1

MD0

EXTAL

XTAL

PLLVCC

PLLCAP

PLLVSS

STBY

RES

WDTOVF

NMI

FWE*

H8S/2600 CPU

DTC

Interrupt controller

Port 4

Port 1

Note: * The FWE pin is used only in the flash memory version.

Port E

Figure 1.1 Internal Block Diagram (H8S/2623 Group)

HD64F2621 Datasheet(PDF) 30 Page - Renesas Technology Corp

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