HD64F2621 datasheet(10/1069 Pages) RENESAS

10 / 1069 page

Rev. 5.00 Jan 10, 2006 page x of xxiv

2.8.5

Bus-Released State...............................................................................................

2.8.6

Power-Down State ...............................................................................................

2.9

Basic Timing .....................................................................................................................

2.9.1

Overview..............................................................................................................

2.9.2

On-Chip Memory (ROM, RAM) .........................................................................

2.9.3

On-Chip Supporting Module Access Timing ......................................................

2.9.4

On-Chip HCAN Module Access Timing .............................................................

2.9.5

External Address Space Access Timing ..............................................................

2.10

Usage Note........................................................................................................................

2.10.1 TAS Instruction....................................................................................................

Section 3 MCU Operating Modes .................................................................................. 73

3.1

Overview...........................................................................................................................

3.1.1

Operating Mode Selection ...................................................................................

3.1.2

3.2

Register Descriptions ........................................................................................................75

3.2.1

Mode Control Register (MDCR) .........................................................................

3.2.2

System Control Register (SYSCR) ......................................................................

3.2.3

Pin Function Control Register (PFCR) ................................................................

3.3

Operating Mode Descriptions ...........................................................................................

3.3.1

Mode 4 .................................................................................................................

3.3.2

Mode 5 .................................................................................................................

3.3.3

Mode 6 .................................................................................................................

3.3.4

Mode 7 .................................................................................................................

3.4

Pin Functions in Each Operating Mode ............................................................................

3.5

Address Map in Each Operating Mode .............................................................................

Section 4 Exception Handling ......................................................................................... 85

4.1

Overview...........................................................................................................................

4.1.1

Exception Handling Types and Priority ...............................................................

4.1.2

Exception Handling Operation.............................................................................

4.1.3

Exception Vector Table .......................................................................................

4.2

Reset..................................................................................................................................

4.2.1

Overview..............................................................................................................

4.2.2

Reset Sequence ....................................................................................................

4.2.3

Interrupts after Reset............................................................................................

4.2.4

State of On-Chip Supporting Modules after Reset Release .................................

4.3

Traces................................................................................................................................

4.4

Interrupts ...........................................................................................................................

4.5

Trap Instruction.................................................................................................................

4.6

Stack Status after Exception Handling..............................................................................

HD64F2621 Datasheet(PDF) 10 Page - Renesas Technology Corp

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