HD64F2621 datasheet(21/1069 Pages) RENESAS

21 / 1069 page

Rev. 5.00 Jan 10, 2006 page xxi of xxiv

19.7.1 Program Mode ..................................................................................................... 651

19.7.2 Program-Verify Mode.......................................................................................... 652

19.7.3 Erase Mode .......................................................................................................... 656

19.7.4 Erase-Verify Mode .............................................................................................. 656

19.8

Protection .......................................................................................................................... 658

19.8.1 Hardware Protection ............................................................................................ 658

19.8.2 Software Protection.............................................................................................. 659

19.8.3 Error Protection.................................................................................................... 660

19.9

Flash Memory Emulation in RAM ................................................................................... 662

19.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 664

19.11 Flash Memory Programmer Mode .................................................................................... 664

19.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 665

19.11.2 Programmer Mode Operation .............................................................................. 667

19.11.3 Memory Read Mode ............................................................................................ 668

19.11.4 Auto-Program Mode ............................................................................................ 672

19.11.5 Auto-Erase Mode ................................................................................................. 674

19.11.6 Status Read Mode ................................................................................................ 676

19.11.7 Status Polling ....................................................................................................... 677

19.11.8 Programmer Mode Transition Time .................................................................... 677

19.11.9 Notes on Memory Programming.......................................................................... 678

19.12 Flash Memory and Power-Down States............................................................................ 679

19.12.1 Note on Power-Down States ................................................................................ 679

19.13 Flash Memory Programming and Erasing Precautions ..................................................... 680

19.14 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 685

Section 20 Clock Pulse Generator .................................................................................. 687

20.1

Overview........................................................................................................................... 687

20.1.1 Block Diagram ..................................................................................................... 688

20.1.2 Register Configuration......................................................................................... 688

20.2

Register Descriptions ........................................................................................................ 689

20.2.1 System Clock Control Register (SCKCR) ........................................................... 689

20.2.2 Low-Power Control Register (LPWRCR) ........................................................... 690

20.3

Oscillator........................................................................................................................... 691

20.3.1 Connecting a Crystal Resonator........................................................................... 691

20.3.2 External Clock Input ............................................................................................ 694

20.4

PLL Circuit ....................................................................................................................... 696

20.5

Medium-Speed Clock Divider .......................................................................................... 696

20.6

Bus Master Clock Selection Circuit .................................................................................. 697

20.7

Subclock Oscillator (H8S/2626 Group Only) ................................................................... 697

20.8

Subclock Waveform Shaping Circuit (H8S/2626 Group Only)........................................ 698

20.9

Note on Crystal Resonator ................................................................................................ 698

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