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HD64F2621 Datasheet(PDF) 29 Page - Renesas Technology Corp |
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HD64F2621 Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 1069 page  Section 1 Overview Rev. 5.00 Jan 10, 2006 page 5 of 1042 REJ09B0275-0500 Item Specifications Operating modes • Four MCU operating modes External Data Bus Mode CPU Operating Mode Description On-Chip ROM Initial Width Max. Width 4 Advanced On-chip ROM disabled expansion mode Disabled 16 bits 16 bits 5 On-chip ROM disabled expansion mode Disabled 8 bits 16 bits 6 On-chip ROM enabled expansion mode Enabled 8 bits 16 bits 7 Single-chip mode Enabled — — Clock pulse generator • Built-in PLL circuit (×1, ×2, ×4) • Input clock frequency: 2 to 20 MHz Package • 100-pin plastic QFP (FP-100B) Product lineup Model Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Package HD6432626 HD6432623 HD64F2626 HD64F2623 256 k/12 k FP-100B HD6432625 HD6432622 — 128 k/8 k FP-100B HD6432624 HD6432621 — 64 k/4 k FP-100B |
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