HD64F2621 datasheet(13/1069 Pages) RENESAS

13 / 1069 page

Rev. 5.00 Jan 10, 2006 page xiii of xxiv

7.6

Idle Cycle .......................................................................................................................... 174

7.6.1

Operation ............................................................................................................. 174

7.6.2

Pin States in Idle Cycle ........................................................................................ 176

7.7

Write Data Buffer Function .............................................................................................. 177

7.8

Bus Release ....................................................................................................................... 178

7.8.1

Overview.............................................................................................................. 178

7.8.2

Operation ............................................................................................................. 178

7.8.3

Pin States in External Bus Released State............................................................ 179

7.8.4

Transition Timing ................................................................................................ 180

7.8.5

Usage Note........................................................................................................... 181

7.9

Bus Arbitration.................................................................................................................. 181

7.9.1

Overview.............................................................................................................. 181

7.9.2

Operation ............................................................................................................. 181

7.9.3

Bus Transfer Timing ............................................................................................ 182

7.10

Resets and the Bus Controller ........................................................................................... 182

Section 8 Data Transfer Controller (DTC)................................................................... 183

8.1

Overview........................................................................................................................... 183

8.1.1

Features................................................................................................................ 183

8.1.2

Block Diagram ..................................................................................................... 184

8.1.3

8.2

Register Descriptions ........................................................................................................ 186

8.2.1

DTC Mode Register A (MRA) ............................................................................ 186

8.2.2

DTC Mode Register B (MRB)............................................................................. 188

8.2.3

DTC Source Address Register (SAR).................................................................. 189

8.2.4

DTC Destination Address Register (DAR).......................................................... 189

8.2.5

DTC Transfer Count Register A (CRA) .............................................................. 190

8.2.6

DTC Transfer Count Register B (CRB)............................................................... 190

8.2.7

DTC Enable Registers (DTCER) ......................................................................... 191

8.2.8

DTC Vector Register (DTVECR)........................................................................ 192

8.2.9

Module Stop Control Register A (MSTPCRA) ................................................... 193

8.3

Operation .......................................................................................................................... 193

8.3.1

Overview.............................................................................................................. 193

8.3.2

Activation Sources ............................................................................................... 195

8.3.3

DTC Vector Table................................................................................................ 197

8.3.4

Location of Register Information in Address Space ............................................ 200

8.3.5

Normal Mode....................................................................................................... 201

8.3.6

Repeat Mode ........................................................................................................ 202

8.3.7

Block Transfer Mode ........................................................................................... 203

8.3.8

Chain Transfer ..................................................................................................... 205

8.3.9

Operation Timing................................................................................................. 206

HD64F2621 Datasheet(PDF) 13 Page - Renesas Technology Corp

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