HD64F2621 datasheet(58/1069 Pages) RENESAS

58 / 1069 page

Section 2 CPU

Rev. 5.00 Jan 10, 2006 page 34 of 1042

REJ09B0275-0500

Free area

Stack area

SP (ER7)

Figure 2.9 Stack

2.4.3

Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC).

(1) Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length

of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an

instruction is fetched, the least significant PC bit is regarded as 0.)

(2) Extended Control Register (EXR)

This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed

in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is

executed.

Bits 6 to 3—Reserved: They are always read as 1.

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to

7). For details, refer to section 5, Interrupt Controller.

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. All interrupts, including NMI, are disabled for three states after one of these

instructions is executed, except for STC.

HD64F2621 Datasheet(PDF) 58 Page - Renesas Technology Corp