HD64F2621 datasheet(25/1069 Pages) RENESAS

25 / 1069 page

Section 1 Overview

Rev. 5.00 Jan 10, 2006 page 1 of 1042

REJ09B0275-0500

Section 1 Overview

1.1

Overview

The H8S/2626 Group and H8S/2623 Group are series of microcomputers (MCUs) that integrate

peripheral functions required for system configuration together with an H8S/2600 CPU employing

an original Renesas architecture.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general

registers and a concise, optimized instruction set designed for high-speed operation, and can

address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300

and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,

H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include a data transfer controller

(DTC) bus master, ROM and RAM, a16-bit timer-pulse unit (TPU), programmable pulse

generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area

network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports.

The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte mask

ROM. The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word data

to be accessed in one state. Instruction fetching has been speeded up, and processing speed

increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or

external expansion mode.

The features of the H8S/2626 Group and H8S/2623 Group are shown in table 1.1.

Note: *

F-ZTAT is a trademark of Renesas Technology Corp.

HD64F2621 Datasheet(PDF) 25 Page - Renesas Technology Corp