HD64F2621 datasheet(89/1069 Pages) RENESAS

89 / 1069 page

Section 2 CPU

Rev. 5.00 Jan 10, 2006 page 65 of 1042

REJ09B0275-0500

2.8.4

Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5

Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. While the bus is released, the CPU halts operations.

Bus masters other than the CPU are data transfer controller (DTC).

For further details, refer to section 7, Bus Controller.

2.8.6

Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,

software standby mode, hardware standby mode, subsleep mode*, and watch mode*. There are

also three other power-down modes: medium-speed mode, module stop mode, and subactive

mode*. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.

Module stop mode permits halting of the operation of individual modules, other than the CPU.

Subactive mode*, subsleep mode*, and watch mode* are power-down states using subclock input.

For details, refer to section 21B, Power-Down Modes [H8S/2626 Group].

Note: *

Supported only in the H8S/2626 Group; not available in the H8S/2623 Group.

HD64F2621 Datasheet(PDF) 89 Page - Renesas Technology Corp