H83065 datasheet(170/963 Pages) RENESAS

170 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 148 of 938

REJ09B0276-0400

Table 6.3

Bus Specifications for Each Area (Basic Bus Interface)

ABWCR ASTCR

WCRH/WCRL

Bus Specifications (Basic Bus Interface)

ABWn

ASTn

Wn1

Wn0

Bus Width

Access States

Program Wait States

——

100

——

100

Note:

n = 7 to 0

6.3.3

Memory Interfaces

The H8/3067 Group memory interfaces comprise a basic bus interface that allows direct

connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of

DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can

be selected independently for each area.

An area for which the basic bus interface is designated functions as normal space, an area for

which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst

ROM interface is designated functions as burst ROM space.

6.3.4

Chip Select Signals

For each of areas 0 to 7, the H8/3067 Group can output a chip select signal (

0 to CS7) that goes

low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output

timing of a

CSn signal.

Output of

0 to CS

3: Output of CS0 to CS3 is enabled or disabled in the data direction register

(DDR) of the corresponding port.

In the expanded modes with on-chip ROM disabled, a reset leaves pin

0 in the output state and

pins

1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding DDR

bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins

0 to

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