H83065 datasheet(172/963 Pages) RENESAS

172 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 150 of 938

REJ09B0276-0400

6.3.5

Address Output Method

The H8/3067 Group provides a choice of two address update methods: either the same method as

in the previous H8/300H Series (address update mode 1), or a method in which address update is

restricted to external space accesses or self-refresh cycles (address update mode 2).

Figure 6.5 shows examples of address output in these two update modes.

On-chip

memory cycle

On-chip

memory cycle

External

read cycle

On-chip

memory cycle

External

read cycle

Address update

mode 1

Address update

mode 2

Figure 6.5 Sample Address Output in Each Address Update Mode

(Basic Bus Interface, 3-State Space)

Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H

Series. Addresses are always updated between bus cycles.

Address Update Mode 2: In address update mode 2, address updating is performed only in

external space accesses or self-refresh cycles. In this mode, the address can be retained between an

external space read cycle and an instruction fetch cycle (on-chip memory) by placing the program

in on-chip memory. Address update mode 2 is therefore useful when connecting a device that

requires address hold time with respect to the rise of the

RD strobe.

Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in

ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing

compatibility with the previous H8/300H Series.

Cautions: The address output methods are designed so that the initial state with the bit selection

method is compatible with the flash memory version (HD64F3067) (i.e. address update mode 1),

and so there is basically no problem if this version is replaced with the flash memory R version or

a mask ROM version. However, the following points should be noted.

H83065 Datasheet(PDF) 172 Page - Renesas Technology Corp