H83065 datasheet(173/963 Pages) RENESAS

173 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 151 of 938

REJ09B0276-0400

• ADRCR is allocated to address H'FEE01E. In the flash memory version, the corresponding

address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E

in the program.

• When address update mode 2 is selected, the address in an internal space (on-chip memory or

internal I/O) access cycle is not output externally.

• In order to secure address holding with respect to the rise of RD, when address update mode 2

is used an external space read access must be completed within a single access cycle. For

example, in a word access to 8-bit access space, the bus cycle is split into two as shown in

figure 6.6., and so there is not a single access cycle. In this case, address holding is not

guaranteed at the rise of

RD between the first (even address) and second (odd address) access

cycles (area inside the ellipse in the figure).

On-chip

memory cycle

On-chip

memory cycle

External read cycle

(8-bit space word access)

Address update

mode 2

Even address

Odd address

Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2

• When address update mode 2 is selected, in a DRAM space CAS-before-RAS (CBR) refresh

cycle the previous address is retained (the area 2 start address is not output).

H83065 Datasheet(PDF) 173 Page - Renesas Technology Corp