SH7014 datasheet(348/754 Pages) RENESAS

348 / 754 page

12. Serial Communication Interface (SCI)

Rev.5.00 Sep. 27, 2007 Page 314 of 716

REJ09B0398-0500

Bit 4

⎯Receive Enable (RE): Enables or disables the SCI serial receiver.

Bit 4

Description

Receiver disabled*

(initial value)

Receiver enabled*

Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These

flags retain their previous values.

2. Serial reception starts when a start bit is detected in the asynchronous mode, or

synchronous clock input is detected in the clock synchronous mode. Select the receive

format in the SMR before setting RE to 1.

Bit 3

⎯Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit

(MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in

the clock synchronous mode or when the MP bit is cleared to 0.

Bit 3

MPIE

Description

Multiprocessor interrupts are disabled (normal receive operation)

(initial value)

MPIE is cleared when the MPIE bit is cleared to 0, or the multiprocessor

bit (MPB) is set to 1 in receive data.

Multiprocessor interrupts are enabled*

Receive-data-full interrupt requests (RXI), receive-error interrupt

requests (ERI), and setting of the RDRF, FER, and ORER status flags

in the serial status register (SSR) are disabled until data with the

multiprocessor bit set to 1 is received.

Note:

The SCI does not transfer receive data from the RSR to the RDR, does not detect

receive errors, and does not set the RDRF, FER, and ORER flags in the serial status

SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and

RIE bits in the SCR are set to 1), and allows the FER and ORER bits to be set.

SH7014 Datasheet(PDF) 348 Page - Renesas Technology Corp