7534 datasheet(8/221 Pages) RENESAS

8 / 221 page

List of figures

7534 Group

Rev.3.00

Oct 23, 2006

page 4 of 9

REJ09B0178-0300

List of figures

CHAPTER 1 HARDWARE

Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP .................................................... 2

Fig. 2 Pin configuration of M37534M4-XXXGP, M37534E4GP .................................................. 3

Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP ........................... 4

Fig. 4 Functional block diagram (PRSP0036GA-A package type) ............................................. 5

Fig. 5 Functional block diagram (PLQP0032GB-A package type) ............................................. 6

Fig. 6 Functional block diagram (PRDP0042BA-A package type) ............................................. 7

Fig. 7 Memory expansion plan ........................................................................................................ 9

Fig. 8 740 Family CPU register structure .................................................................................... 10

Fig. 9 Register push and pop at interrupt generation and subroutine call ............................ 11

Fig. 10 Structure of CPU mode register ...................................................................................... 13

Fig. 11 Switching method of CPU mode register ....................................................................... 13

Fig. 12 Memory map diagram ....................................................................................................... 14

Fig. 13 Memory map of special function register (SFR) ........................................................... 15

Fig. 14 Structure of pull-up control register ................................................................................ 16

Fig. 15 Structure of port P1P3 control register .......................................................................... 16

Fig. 16 Block diagram of ports (1) ............................................................................................... 18

Fig. 17 Block diagram of ports (2) ............................................................................................... 19

Fig. 18 Interrupt control .................................................................................................................. 21

Fig. 19 Structure of Interrupt-related registers ........................................................................... 21

Fig. 20 Connection example when using key input interrupt and port P0 block diagram ... 22

Fig. 21 Structure of timer X mode register ................................................................................. 23

Fig. 22 Timer count source set register ...................................................................................... 23

Fig. 23 Block diagram of timer X, timer 1 and timer 2 ............................................................. 24

Fig. 24 Block diagram of UART serial I/O1 ................................................................................ 25

Fig. 25 Operation of UART serial I/O1 function ......................................................................... 25

Fig. 26 Continuous transmission operation of UART serial I/O ............................................... 26

Fig. 27 USB mode block diagram ................................................................................................ 27

Fig. 28 USB transceiver block diagram ....................................................................................... 27

Fig. 29 Structure of serial I/Orelated registers (1) ..................................................................... 28

Fig. 30 Structure of serial I/O1-related registers (2) ................................................................. 29

Fig. 31 Structure of serial I/O1-related registers (3) ................................................................. 30

Fig. 32 Structure of serial I/O1-related registers (4) ................................................................. 31

Fig. 33 Structure of serial I/O1-related registers (5) ................................................................. 32

Fig. 34 Structure of serial I/O2 control registers ........................................................................ 34

Fig. 35 Block diagram of serial I/O2 ............................................................................................ 34

Fig. 36 Serial I/O2 timing (LSB first) ........................................................................................... 35

Fig. 37 Structure of A/D control register ..................................................................................... 36

Fig. 38 Structure of A/D conversion register .............................................................................. 36

Fig. 39 Block diagram of A/D converter ...................................................................................... 36

Fig. 40 Block diagram of watchdog timer .................................................................................... 37

Fig. 41 Structure of watchdog timer control register ................................................................. 37

Fig. 42 Example of reset circuit .................................................................................................... 38

Fig. 43 Timing diagram at reset ................................................................................................... 38

Fig. 44 Internal status of microcomputer at reset ...................................................................... 39

Fig. 45 External circuit of ceramic resonator .............................................................................. 40

Fig. 46 External clock input circuit ............................................................................................... 40

Fig. 47 Structure of MISRG ........................................................................................................... 40

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