7534 datasheet(33/221 Pages) RENESAS

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HARDWARE

7534 Group

FUNCTIONAL DESCRIPTION

Rev.3.00

Oct 23, 2006

page 20 of 55

REJ09B0178-0300

Interrupt operation

Upon acceptance of an interrupt the following operations are auto-

matically performed:

1. The processing being executed is stopped.

2. The contents of the program counter and processor status regis-

ter are automatically pushed onto the stack.

3. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

4. Concurrently with the push operation, the interrupt destination

address is read from the vector table into the program counter.

Notes on use

When the active edge of an external interrupt (INT0, INT1, CNTR0) is

set, the interrupt request bit may be set.

Therefore, please take following sequence:

1. Disable the external interrupt which is selected.

2. Change the active edge in interrupt edge selection register. (in

case of CNTR0: Timer X mode register)

3. Clear the set interrupt request bit to “0”.

4. Enable the external interrupt which is selected.

Remarks

Non-maskable

Valid in UART mode

Valid in USB mode

Valid in UART mode

Valid in USB mode

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt (valid at falling)

STP release timer underflow

External interrupt (active edge

selectable)

Non-maskable software interrupt

Note 1: Vector addressed contain internal jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Interrupts

Interrupts occur by 14 different sources : 4 external sources, 9 inter-

nal sources and 1 software source.

Interrupt control

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit, and they are controlled by the

interrupt disable flag. When the interrupt enable bit and the interrupt

request bit are set to “1” and the interrupt disable flag is set to “0”, an

interrupt is accepted.

The interrupt request bit can be cleared by program but not be set.

The interrupt enable bit can be set and cleared by program.

It becomes usable by switching CNTR0 and A/D interrupt sources

with bit 7 of the interrupt edge selection register, timer 2 and serial I/

O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt

sources with bit 5, and serial I/O transmit and INT1 interrupt sources

with bit 4.

The reset and BRK instruction interrupt can never be disabled with

any flag or bit. All interrupts except these are disabled when the in-

terrupt disable flag is set.

When several interrupts occur at the same time, the interrupts are

received according to priority.

Table 6 Interrupt vector address and priority

Vector addresses (Note 1)

High-order

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

Priority

Low-order

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

Interrupt request generating conditions

At reset input

At completion of UART data receive

At detection of IN token

At completion of UART transmit shift or

when transmit buffer is empty

At detection of SETUP/OUT token or

At detection of Reset/ Suspend/ Resume

At detection of either rising or falling edge

of INT1 input

At detection of either rising or falling edge

of INT0 input

At timer X underflow

At falling of conjunction of input logical

level for port P0 (at input)

At timer 1 underflow

At timer 2 underflow

At completion of transmit/receive shift

At detection of either rising or falling edge

of CNTR0 input

At completion of A/D conversion

At BRK instruction execution

Interrupt source

Reset (Note 2)

UART receive

USB IN token

UART transmit

USB SETUP/OUT token

Reset/Suspend/Resume

INT1

INT0

Timer X

Key-on wake-up

Timer 1

Timer 2

Serial I/O2

CNTR0

A/D conversion

BRK instruction

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