7534 datasheet(10/221 Pages) RENESAS

10 / 221 page

List of figures

7534 Group

Rev.3.00

Oct 23, 2006

page 6 of 9

REJ09B0178-0300

Fig. 2.3.5 Structure of UART control register ............................................................................. 31

Fig. 2.3.6 Structure of Baud rate generator ................................................................................ 31

Fig. 2.3.7 Structure of Serial I/O2 control register ..................................................................... 32

Fig. 2.3.8 Structure of Serial I/O2 register .................................................................................. 32

Fig. 2.3.9 Structure of Interrupt edge selection register ........................................................... 33

Fig. 2.3.10 Structure of Interrupt request register 1 .................................................................. 33

Fig. 2.3.11 Structure of Interrupt control register 1 ................................................................... 34

Fig. 2.3.12 Serial I/O connection examples (1) .......................................................................... 35

Fig. 2.3.13 Serial I/O connection examples (2) .......................................................................... 36

Fig. 2.3.14 Serial I/O transfer data format .................................................................................. 37

Fig. 2.3.15 Connection diagram .................................................................................................... 38

Fig. 2.3.16 Timing chart ................................................................................................................. 38

Fig. 2.3.17 Registers setting relevant to transmission side ...................................................... 39

Fig. 2.3.18 Transmission data setting of serial I/O2 .................................................................. 40

Fig. 2.3.19 Registers setting relevant to reception side ............................................................ 40

Fig. 2.3.20 Control procedure of transmission side ................................................................... 41

Fig. 2.3.21 Control procedure of reception side ......................................................................... 42

Fig. 2.3.22 Connection diagram .................................................................................................... 43

Fig. 2.3.23 Timing chart ................................................................................................................. 43

Fig. 2.3.24 Registers setting relevant to transmission side ...................................................... 45

Fig. 2.3.25 Registers setting relevant to reception side ............................................................ 46

Fig. 2.3.26 Control procedure of transmission side ................................................................... 47

Fig. 2.3.27 Control procedure of reception side ......................................................................... 48

Fig. 2.3.28 Sequence of clearing serial I/O ................................................................................ 49

Fig. 2.4.1 Communication sequence of USB .............................................................................. 51

Fig. 2.4.2 Data structure of USB packet ..................................................................................... 52

Fig. 2.4.3 USB (L.S.) interface ...................................................................................................... 55

Fig. 2.4.4 USB (L.S.) connection example .................................................................................. 55

Fig. 2.4.5 Memory map of registers relevant to USB ................................................................ 56

Fig. 2.4.6 Description of the register structure ........................................................................... 57

Fig. 2.4.7 Register structures relevant to USB (1) .................................................................... 58

Fig. 2.4.8 Register structures relevant to USB (2) .................................................................... 59

Fig. 2.4.9 Register structures relevant to USB (3) .................................................................... 60

Fig. 2.4.10 Register structures relevant to USB (4) .................................................................. 61

Fig. 2.4.11 Control method of control sequence ........................................................................ 62

Fig. 2.4.12 Timing chart of the transaction according to each token ..................................... 63

Fig. 2.4.13 USB interrupt processing example (OUT token) .................................................... 65

Fig. 2.4.14 USB interrupt processing example (IN token) ........................................................ 66

Fig. 2.4.15 Data read timing of SETUP token ............................................................................ 67

Fig. 2.4.16 Data read timing of OUT token ................................................................................ 67

Fig. 2.4.17 Data read timing of IN token (endpoint 0) and IN token (endpoint 1) token .... 67

Fig. 2.4.18 Timing chart of each signal ....................................................................................... 68

Fig. 2.4.19 Example for determination of resume interrupt ...................................................... 69

Fig. 2.4.20 Processing for width of SE0 signal .......................................................................... 69

Fig. 2.4.21 Countermeasure (2) by software .............................................................................. 70

Fig. 2.5.1 Memory map of registers relevant to A/D converter ................................................ 71

Fig. 2.5.2 Structure of A/D control register ................................................................................. 71

Fig. 2.5.3 Structure of A/D conversion register (high-order) .................................................... 72

Fig. 2.5.4 Structure of A/D conversion register (low-order) ...................................................... 72

Fig. 2.5.5 Structure of Interrupt edge selection register ........................................................... 73

Fig. 2.5.6 Structure of Interrupt request register 1 .................................................................... 73

Fig. 2.5.7 Structure of Interrupt control register 1 ..................................................................... 74

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