7534 datasheet(11/221 Pages) RENESAS

11 / 221 page

7534 Group

List of figures

Rev.3.00

Oct 23, 2006

page 7 of 9

REJ09B0178-0300

Fig. 2.5.8 Connection diagram ...................................................................................................... 75

Fig. 2.5.9 Relevant registers setting ............................................................................................ 75

Fig. 2.5.10 Control procedure for 8-bit read ............................................................................... 76

Fig. 2.5.11 Control procedure for 10-bit read ............................................................................. 76

Fig. 2.5.12 Method to stabilize A/D conversion accuracy ......................................................... 77

Fig. 2.6.1 Example of poweron reset circuit ............................................................................... 78

CHAPTER 3 APPENDIX

Fig. 3.1.1 Power source current measurement circuit in USB mode at oscillation stop ........ 5

Fig. 3.1.2 Output switching characteristics measurement circuit ............................................... 6

Fig. 3.1.3 Timing chart ..................................................................................................................... 7

Fig. 3.2.1 ICC-VCC characteristic example (in double-speed mode) ............................................. 8

Fig. 3.2.2 ICC-VCC characteristic example (at WIT instruction execution) .................................. 8

Fig. 3.2.3 ICC-VCC characteristic example (At STP instruction execution, Ta = 25 °C) ........... 9

Fig. 3.2.4 ICC-VCC characteristic example (At STP instruction execution, Ta = 85 °C) ........... 9

Fig. 3.2.5 ICC-VCC characteristic example (at USB suspend, Ta = 25 °C) .............................. 10

Fig. 3.2.6 ICC-VCC characteristic example (A/D conversion executed/not executed, f(XIN) = 6MHz,

in double-speed mode) ................................................................................................. 10

Fig. 3.2.7 VOH-IOH characteristic example of P-channel (Ta = 25 °C): normal port ............... 11

Fig. 3.2.8 VOH-IOH characteristic example of P-channel (Ta = 85 °C): normal port ............... 11

Fig. 3.2.9 VOL-IOL characteristic example of N-channel (Ta = 25 °C): Normal port ............... 12

Fig. 3.2.10 VOL-IOL characteristic example of N-channel (Ta = 85 °C): Normal port ............. 12

Fig. 3.2.11 VOL-IOL characteristic example of N-channel (Ta = 25 °C): LED drive port ........ 13

Fig. 3.2.12 VOL-IOL characteristic example N-channel (Ta = 85 °C): LED drive port ............. 13

Fig. 3.2.13 “L” input current of port at pull-up transistor connected ....................................... 14

Fig. 3.2.14 Definition of A/D conversion accuracy ..................................................................... 15

Fig. 3.2.15 A/D conversion typical characteristic example ........................................................ 16

Fig. 3.3.1 Sequence of switch the detection edge ..................................................................... 17

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................... 17

Fig. 3.3.3 Structure of interrupt control register 1 ..................................................................... 18

Fig. 3.3.4 Sequence of clearing serial I/O .................................................................................. 18

Fig. 3.3.5 Method to stabilize A/D conversion accuracy ........................................................... 19

Fig. 3.3.6 Initialization of processor status register ................................................................... 21

Fig. 3.3.7 Sequence of PLP instruction execution ..................................................................... 21

Fig. 3.3.8 Stack memory contents after PHP instruction execution ........................................ 21

Fig. 3.3.9 Status flag at decimal calculations ............................................................................. 22

Fig. 3.3.10 Programming and testing of One Time PROM version ......................................... 22

Fig. 3.3.11 Switching method of CPU mode register ................................................................ 25

Fig. 3.3.12 Countermeasure (2) by software .............................................................................. 26

Fig. 3.4.1 Selection of packages .................................................................................................. 27

_____________

Fig. 3.4.2 Wiring for the RESET pin ............................................................................................ 27

Fig. 3.4.3 Wiring for clock I/O pins .............................................................................................. 28

Fig. 3.4.4 Wiring for CNVSS pin ................................................................................................... 28

Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM ........................................................ 29

Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................... 29

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................... 30

Fig. 3.4.8 Wiring for a large current signal line ......................................................................... 30

Fig. 3.4.9 Wiring of signal lines where potential levels change frequently ............................ 31

Fig. 3.4.10 VSS pattern on the underside of an oscillator .......................................................... 31

Fig. 3.4.11 Setup for I/O ports ...................................................................................................... 32

Fig. 3.4.12 Watchdog timer by software ...................................................................................... 33

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