SH7713 datasheet(385/904 Pages) RENESAS

385 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 345 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

HIZCNT

R/W

High-Z Control

Specifies the state in standby mode and bus released for

CKIO, CKIO2, CKE,

RAS, and CAS.

0: High impedance in standby mode and bus released for

CKIO, CKIO2, CKE,

RAS, and CAS.

1: Driven in standby mode and bus released for CKIO,

CKIO2, CKE,

RAS, and CAS.

Note: If one of clock operating modes 4 to 6 is set, CKIO,

CKIO2, CKE,

RAS, and CAS should be driven in

standby mode and bus released.

Note:

The external pin (MD5) for specifying endian is sampled on power-on reset. When big

endian is specified, this bit is read as 0 and when little endian is specified, this bit is

read as 1.

12.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)

CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and

the number of wait cycles between access cycles.

Do not access external memory other than area 0 until the CSnBCR initialization is completed.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should always

be 0.

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