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SH7713 Datasheet(PDF) 609 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 609 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev.1.50 Aug. 30, 2006 Page 569 of 860
REJ09B0288-0150
Receive error handling
Break handling
Read receive data in SCFRDR
Clear DR, ER, and BRK flags
in SCFSR and ORER flag
in SCLSR to 0
1. Whether a framing error or parity error has
occurred in the receive data read from
SCFRDR can be ascertained from the FER
and PER bits in SCFSR.
2. When a break signal is received, receive
data is not transferred to SCFRDR while
the BRK flag is set. However, note that the
last data in SCFRDR is H'00 and the break
data in which a framing error occurred is
stored.
Error handling
End
ER = 1?
No
Yes
Overrun error handling
No
Yes
BRK = 1?
No
Yes
DR = 1?
No
Yes
ORER = 1?
Figure 16.7 Sample Serial Reception Flowchart (2)



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