SH7713 datasheet(613/904 Pages) RENESAS

613 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 573 of 860

REJ09B0288-0150

In clock synchronous mode, the SCIF receives data in synchronization with the rise of the serial

clock.

Data Transfer Format: A fixed 8-bit data format is used. No parity bit is added.

Clock: An internal clock generated by the on-chip baud rate generator or an external synchronous

clock input from the SCIFnCK pin can be selected, according to the setting of the C/

A bit in

SCSMR and bits CKE1 and CKE0 in SCSCR. For details, see table 16.4.

When the SCIF is operated on an internal clock, synchronous clock is output from the SCIFnCK

pin. Eight serial clock pulses are output in the transfer of one character, and when no

transmission/reception is performed the clock is fixed high. If an internal clock is selected when

only reception is performed, clock pulse is output continuously until the number of data bytes in

the receive FIFO reaches the receive trigger set number while the RE bit in SCSCR is 1.

Data Transfer Operations:

The SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE

and RE bits in SCSCR to 0, then initialize the SCIF as described below.

When the mode, communication format etc., is changed, the TE and RE bits must be cleared to 0

before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR

is initialized. Note that the RDF, PER, FER, and ORER flags and contents of SCFRDR are

retained even if the RE bit is cleared to 0.

SH7713 Datasheet(PDF) 613 Page - Renesas Technology Corp