SH7713 datasheet(614/904 Pages) RENESAS

614 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 574 of 860

REJ09B0288-0150

Figure 16.12 shows a sample the SCIF initialization flowchart.

Wait

Start Initialization

Keep the TE and RE bits cleared to 0 until initialization

has been completed.

Set the CKE1 and CKE0 bits.

Set the transfer or receive format in SCSMR.

Write a value corresponding to the bit rate in SCBRR.

(Not necessary if an external clock is used.) After this

setting wait for at least 1-bit interval.

Set the external pins. Specifies the pins as RxD input

in reception and TxD output in transmission. Set the

SCIFnCK input/output according to the CKE1 and

CKE0 settings.

Set the TE bit or RE bit in SCSCR to 1. Also, set the

TIE, RIE, and REIE bits. At this time, the TxD, RxD,

and SCIFnCK pins can be used. In transmission, the

TxD pin is in the mark state. When reception in

clock synchronous mode and synchronous clock output

(clock master) are selected, a clock is output from the

SCIFnCK pin.

Set transmit or receive format in SCSMR

Set TFRST and RFRST bits in SCFCR

to 1 and clear buffer of FIFO

Read BRK, DR, and ER flags in SCFSR

and clear the flags by writing 0

Yes

Set value in SCBRR

Clear TE and RE bits in SCSCR to 0

Set TE and RE bits in SCSCR to 1

and set RIE, TIE, and REIE bits

Set RTRG1, RTRG0, TTRG1, and

TTRG0 bits in SCFCR. Clear TFRST

and RFRST bits to 0.

1-bit interval elapsed?

End

Set CKE1 and CKE0 bits in SCSCR

(TE, RE, TIE, and RIE bits are

cleared to 0)

Set external pins (SCIFnCK, TxD, RxD)

Figure 16.12 Sample the SCIF Initialization Flowchart

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