SH7713 datasheet(612/904 Pages) RENESAS

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Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 572 of 860

REJ09B0288-0150

When using a modem function and the receive FIFO (SCFRDR) is at least the number of the

RTS

output trigger, the

RTS signal goes high.

RTS

RTS goes high when receive data is

at least number of

RTS output trigger

0D0

0/1

Start

bit

Receive data

RxD

Parity

bit

Stop

bit

RTS goes low when receive data is

less than number of

RTS output trigger

Figure 16.10

RTS Control Operation

16.4.3

Serial Operation in Clock Synchronous Mode

In clock synchronous mode, the SCIF transmits and receives data synchronizing with clock pulses.

This mode is suitable for high-speed serial communication. In the SCIF, the transmitter and

receiver are independent. Therefore, by sharing the same clock, full-duplex communication can be

performed. Figure 16.11 shows the general format of clock synchronous serial communication.

One unit of transfer data (character or frame)

Serial clock

Serial data

Note: * High except in continuous transmission/reception

LSB

Bit 0

MSB

Don’t care

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 16.11 Data Format in Clock Synchronous Communication

In clock synchronous serial communication, data on the communication line is output from one

fall of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.

In serial communication, each character is output starting with the LSB and ending with the MSB.

After the MSB is output, the communication line remains in the state of the MSB.

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