SH7713 datasheet(743/904 Pages) RENESAS

743 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 703 of 860

REJ09B0288-0150

(a)

Receive Descriptor 0 (RD0)

The user sets the descriptor valid/invalid bit and sets whether the descriptor represents the end of

the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the start of a read by the E-

DMAC. After completion of receive DMA transfer of an Ethernet frame by the E-DMAC, the E-

DMAC disables the descriptor valid/invalid bit and writes status information. This operation is

referred to as write-back.

When using RD0, the user should write desired values to bits 31 and 30 according to the

descriptor configuration. Write 0 to bits 29 to 0.

Bit

Bit Name

Initial

Value

R/W

Description

RACT

R/W

Receive Descriptor Valid/Invalid

Indicates whether the corresponding descriptor is

valid or invalid. To make this bit valid, prepare a

receive buffer (user-specified receive data storage

destination) beforehand, then write 1 to this bit. The

E-DMAC clears this bit to 0 upon completion of data

transfer.

0: Indicates that the receive descriptor is invalid

Indicates the initial setting state, the state after 0 is

written, or (in case the user writes 1 to this bit) that

this bit is cleared to 0 because of completion of the

processing of the E-DMAC data transfer.

If this state is recognized when the E-DMAC reads

a descriptor, the E-DMAC clears the RR bit in

EDRRR to 0, and halts transfer operation related

to reception by the E-DMAC.

1: Indicates that the receive descriptor is valid

Indicates that data is not transferred yet after the

user writes 1 to this bit, or that data is being

transferred.

When there is a descriptor row (descriptor list)

consisting of multiple continuous descriptors, the

E-DMAC can continue operation when this bit of

the next descriptor is valid.

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