SH7713 datasheet(746/904 Pages) RENESAS

746 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 706 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

RFE

R/W

Receive Frame Error Occurrence

Indicates that an error occurred in the receive frame.

The errors occurred in RFS8 (bit 8), or RFS3 to RFS0

(bits 3 to 0). TRSCER can specify whether the

multicast address frame receive information is

reflected in this bit or not.

26 to 0

RFS26 to

RFS0

All 0

R/W

Receive Frame Status

Indicate the status of the corresponding frame. A bit

below, when set to 1, indicates the occurrence of the

corresponding event. If the events of RFS8, or RFS4

to RFS0 occur, frames are incompletely received.

RFS26 to RFS10: Reserved (The write value should

always be 0)

RFS9: Receive FIFO overflow (corresponding to the

RFOF bit in EESR)

RFS8: Receive abort detected

Note: This bit is set when any bit of RFS3 to RFS0

is set.

RFS7: Multicast address frame received

(corresponding to the RMAF bit in EESR)

RFS6 and RFS5: Reserved (The write value should

always be 0)

RFS4: residual-bit frame receive error (corresponding

to the RRF bit in EESR)

RFS3: Too-long frame receive error (corresponding

to the RTLF bit in EESR)

RFS2: Too-short frame receive error (corresponding

to the RTSF bit in EESR)

RFS1: PHY-LSI receive error (corresponding to the

PRE bit in EESR)

RFS0: CRC error on receive frame (corresponding to

the CERF bit in EESR)

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