SH7713 datasheet(749/904 Pages) RENESAS

749 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 709 of 860

REJ09B0288-0150

This LSI + memory

Transmission flowchart

E-DMAC

EtherC

Ethernet

Transmit FIFO

EtherC/E-DMAC

initialization

Transmit

descriptor and

transmit buffer

setting

Start of transmission

Transmit descriptor read

Transmit descriptor

write-back

Transmit descriptor

write-back

Transmission

completed

Transmit descriptor

read

Transmit data transfer

Frame transmission

Transmit data transfer

[Legend]

EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1.

Transmit descriptor and transmit buffer setting: Sets transmit descriptors and transmit buffers, and sets EtherC

and E-DMAC registers, then writes 1 to the TE bit in ECMR

and the TR bit in EDTRR.

Start of transmission: Occurs when 1 is written to the TE bit in ECMR and the TR bit in EDTRR.

Transmit descriptor read: The E-DMAC reads a transmit descriptor.

Transmit data transfer: Writes transmit data to the transmit FIFO by using DMA transfer by the E-DMAC.

Transmit descriptor write-back: The E-DMAC writes 0 to the TACT bit and writes the transmit status to the transmit descriptor.

Figure 19.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor)

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