SH7713 datasheet(751/904 Pages) RENESAS

751 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 711 of 860

REJ09B0288-0150

This LSI + memory

Reception flowchart

E-DMAC

EtherC

Receive FIFO

Ethernet

EtherC/E-DMAC

initialization

Receive

descriptor and

receive buffer

setting

Reception

completed

[Legend]

EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1.

Receive descriptor and receive buffer setting: Sets receive descriptors and receive buffers, and sets EtherC and E-DMAC

registers, then writes 1 to the RE bit in ECMR and the RR bit in EDRRR.

Start of reception: Occurs when 1 is written to the RE bit in ECMR and the RR bit in EDRRR.

Receive descriptor read: The E-DMAC reads a receive descriptor.

Receive data transfer: Writes receive data from the receive FIFO to the receive buffer by using DMA transfer by the E-DMAC.

Receive descriptor write-back: The E-DMAC writes 0 to the RACT bit and writes the receive status to the receive descriptor.

Receive data transfer

Frame reception

Start of reception

Receive descriptor read

Receive descriptor

write-back

Receive descriptor

write-back

Receive descriptor read

(preparation for receiving

the next frame)

Receive descriptor

read

Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor)

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