SH7713 datasheet(754/904 Pages) RENESAS

754 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 714 of 860

REJ09B0288-0150

19.3.5

Receive FIFO Overflow Alert Signal (

ARBUSY)

The E-DMAC outputs the receive FIFO overflow alert signal (

ARBUSY) to the EtherC to support

flow control function conforming to IEEE802.3x of the EtherC. The

ARBUSY signal

synchronized with the bus clock (B clock) signal is also output to an external pin of this LSI.

When the capacity of data received in receive FIFO or the number of receive frames reach the

threshold (RFF2 to RFF0, or RFD2 to RFD0) specified in FCFTR in E-DMAC,

ARBUSY is

valid.

The threshold is the value less than the overflow value: 2048

− 64, 1792 − 32, 1536 − 32,

and 256

− 32 bytes.

Figure 19.8 shows the configuration of the receive FIFO overflow alert signal (

ARBUSY) output.

As shown in figure 19.8, because the

ARBUSY signal passes through the system clock

synchronization circuit, it is behind the receive FIFO overflow alert signal received in EtherC.

This LSI

ARBUSY

EtherC

E-DMAC

Receive FIFO overflow

alert signal

System clock

synchronization

circuit

Figure 19.8 Configuration of

ARBUSY

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