SH7713 datasheet(753/904 Pages) RENESAS

753 / 904 page

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev.1.50 Aug. 30, 2006 Page 713 of 860

REJ09B0288-0150

(2)

Receive Processing in Case of Multi-Buffer Frame

If an error occurs during reception in the case of a multi-buffer frame where a receive frame is

divided for storage in multiple buffers, the E-DMAC performs the processing shown in figure

19.7.

In the figure, the invalid receive descriptors (with the RACT bit cleared to 0) represent the normal

reception of data to be stored in buffers, and the valid receive descriptors (with the RACT bit set

to 1) represent unreceived buffers. If a frame receive error occurs with a descriptor shown in the

figure, the status is written back to the corresponding descriptor.

If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register

(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame

receive request, reception is continued from the buffer after that in which the error occurred.

E-DMAC

Inactivates RACT and writes RFE, RFS

Descriptor read

Descritptors

Buffer length set

by descriptor

Received data

Unreceived data

Receive error

occurrence

Start of frame

New frame reception

continues from this buffer

Frame

type

Start

Continue

Figure 19.7 E-DMAC Operation after Receive Error

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