SH7721 datasheet(545/1524 Pages) RENESAS

545 / 1524 page

Section 13

Power-Down Modes

Rev. 3.00

Jan. 18, 2008

Page 483 of 1458

REJ09B0033-0300

13.3.3

Standby Control Register 3 (STBCR3)

STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-

down mode.

Bit

Bit Name

Initial

Value

R/W

Description

MSTP37

R/W

Module Stop Bit 37

When the MSTP37 bit is set to 1, the supply of the clock

to the SIOF1 is halted.

0: SIOF1 operates

1: Clock supply to SIOF1 halted

MSTP36

R/W

Module Stop Bit 36

When the MSTP36 bit is set to 1, the supply of the clock

to the SIOF0 is halted.

0: SIOF0 operates

1: Clock supply to SIOF0 halted

MSTP35

R/W

Module Stop Bit 35

When the MSTP35 bit is set to 1, the supply of the clock

to the CMT is halted. However, count-up operation is

continued when the channel 5 is in the operation.

0: CMT operates

1: Clock supply to CMT halted



Reserved

This bit is always read as 0. The write value should

always be 0.

MSTP33

R/W

Module Stop Bit 33

When the MSTP33 bit is set to 1, the supply of the clock

to the ADC is halted.

0: ADC operates

1: Clock supply to ADC halted

MSTP32

R/W

Module Stop Bit 32

When the MSTP32 bit is set to 1, the supply of the clock

to the DAC is halted.

0: DAC operates

1: Clock supply to DAC halted

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