SH7721 datasheet(551/1524 Pages) RENESAS

551 / 1524 page

Section 13

Power-Down Modes

Rev. 3.00

Jan. 18, 2008

Page 489 of 1458

REJ09B0033-0300

13.5

Software Standby Mode

13.5.1

Transition to Software Standby Mode

Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the

program execution state to software standby mode. In software standby mode, not only the CPU

but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also

halts.

The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip

peripheral modules are, however, initialized. Refer to section 37, List of Registers, for the register

states of the on-chip peripheral modules in software standby mode. The procedure for a transition

to software standby mode is as follows.

1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.

2. Clear the WDT's timer counter (WTCNT) to 0 and set the CKS2 to CKS0 bits in WTCSR to

appropriate values to secure the specified oscillation settling time.

3. After the STBY bit in STBCR is set to 1, the SLEEP instruction is executed.

4. Software standby mode is entered and the clocks within the chip are halted. The output of the

STATUS0 pin and STATUS1 pin go high and low, respectively.

13.5.2

Canceling Software Standby Mode

Software standby mode is canceled by interrupts (NMI, IRQ (edge detection), RTC, TMU, and

PINT) or a reset.

(1)

Canceling with Interrupt

The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRQ (edge

detection)*

1, RTC*1, TMU*1, or PINT*1 interrupt, the clock will be supplied to the entire chip and

software standby mode will be canceled after the time set in the WDT's timer control/status

then begins and a code indicating the interrupt source is set in INTEVT and INTEVT2. After the

branch to the interrupt handling routine, clear the STBY bit in STBCR. WDT stops automatically.

If the STBY bit is not cleared, WDT continues operation and a transition is made to software

standby mode*

2 when WTCNT reaches H'80. Note that a manual reset is not accepted until the

STBY bit is cleared. Interrupts are accepted in software standby mode even when the BL bit in SR

is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction.

SH7721 Datasheet(PDF) 551 Page - Renesas Technology Corp