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SH7721 Datasheet(PDF) 554 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 554 Page - Renesas Technology Corp |
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554 / 1524 page  Section 13 Power-Down Modes Rev. 3.00 Jan. 18, 2008 Page 492 of 1458 REJ09B0033-0300 13.7 STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timings are shown below. 13.7.1 Reset (1) Power-on reset CKIO STATUS PLL setting time 1. reset : HH (STATUS1 = High, STATUS0 = High) 2. normal : LL (STATUS1 = Low, STATUS0 = Low) 3. Bcyc : Bus clock cycle Notes: *2 *2 *1 0 to 30 Bcyc*3 0 to 5 Bcyc normal reset normal *3 RESETP Figure 13.2 STATUS Output at Power-on Reset (2) Manual reset CKIO STATUS 1. : In manual reset, STATUS = HH (reset) after the current bus cycle is completed and then internal reset is initiated. 2. : reset: HH (STATUS1 = High, STATUS0 = High) 3. : normal: LL (STATUS1 = Low, STATUS0 = Low) 4. : Bcyc: Bus clock cycle Notes *3 *3 *2 0 to 30 Bcyc *4 0Bcyc~ normal reset normal *1,*4 RESETM Figure 13.3 STATUS Output at Manual Reset |
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