SH7721 datasheet(550/1524 Pages) RENESAS

550 / 1524 page

Section 13

Power-Down Modes

Rev. 3.00

Jan. 18, 2008

Page 488 of 1458

REJ09B0033-0300

13.4

Sleep Mode

13.4.1

Transition to Sleep Mode

Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the

program execution state to sleep mode. Although the CPU halts immediately after executing the

SLEEP instruction, the contents of the CPU registers remain unchanged. The on-chip peripheral

modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin.

In sleep mode the output of the STATUS0 pin and STATUS1 pin go high and low, respectively.

13.4.2

Canceling Sleep Mode

Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, and on-chip peripheral module) or

reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save

SPC and SSR to the stack before executing the SLEEP instruction.

(1)

Canceling with Interrupt

When an NMI, IRQ, IRL, PINT, or on-chip peripheral module interrupt occurs, sleep mode is

canceled and interrupt exception handling is executed. A code indicating the interrupt source is set

in INTEVT and INTEVT2.

(2)

Canceling with Reset

Sleep mode is canceled by a power-on reset or a manual reset.

SH7721 Datasheet(PDF) 550 Page - Renesas Technology Corp