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SH7721 Datasheet(PDF) 649 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 649 Page - Renesas Technology Corp |
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649 / 1524 page  Section 18 Serial Communication Interface with FIFO (SCIF) Rev. 3.00 Jan. 18, 2008 Page 587 of 1458 REJ09B0033-0300 Figure 18.1 shows the block diagram of SCIF. Module data bus SCFRDR (64 stages) SCRSR RxD SCFTDR (64 stages) SCTSR SCFDR SCFCR SCFER SCSSR SCSCR SCSMR SCTDSR Clock External clock Parity generation Parity check SCBRR P φ P φ/4 P φ/16 P φ/64 SCIF interrupt SCK CTS RTS TxD SCRSR: SCFRDR: SCTSR: SCFTDR: SCSMR: SCSCR: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFER: SCSSR: SCBRR: SCFCR: SCFDR: SCTDSR: FIFO error count register Serial status register Bit rate register FIFO control register FIFO data count register Transmit data stop register SCIF [Legend] Transmission/ reception control Baud rate generator Figure 18.1 Block Diagram of SCIF |
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