SH7721 datasheet(652/1524 Pages) RENESAS

652 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 590 of 1458

REJ09B0033-0300

18.3.1

Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RxD pin is loaded into the SCRSR in the order

received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,

it is automatically transferred to the SCFRDR, which is a receive FIFO data register. The CPU

cannot read from or write to the SCRSR directly.

18.3.2

Receive FIFO Data Register (SCFRDR)

The 64-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes

the reception of one byte of serial data by moving the received data from the receive shift register

(SCRSR) into the SCFRDR for storage. Continuous receive is enabled until 64 bytes are stored.

The CPU can read but not write the SCFRDR. When data is read without received data in the

SCFRDR, the value is undefined. When the received data in this register becomes full, the

subsequent serial data is lost.

Bit

Bit Name

Initial value

R/W

Description

7 to 0

SCFRD7 to SCFRD0

Undefined

FIFO Data Registers for Serial Receive

Data

18.3.3

Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register

(SCFTDR) into the SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.

After transmitting one data byte, the SCI automatically loads the next transmit data from the

SCFTDR into the SCTSR and starts transmitting again. The CPU cannot read or write the SCTSR

directly.

18.3.4

Transmit FIFO Data Register (SCFTDR)

SCFTDR is a 64-byte 8-bit-length FIFO register that stores data for serial transmission. When the

SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in

the SCFTDR into the SCTSR and starts serial transmission. Continuous serial transmission is

performed until the transmit data in the SCFTDR becomes empty. The CPU can always write to

the SCFTDR.

When the transmit data in the SCFTDR is full (64 bytes), next data cannot be written. If attempted

to write, the data is ignored.

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